1. Field of the Invention
The invention relates to a delay lock loop (DLL), and in particular relates to a low power consumption delay lock loop.
2. Description of the Related Art
Recently, the speeds of very large scale integrated circuits (VLSI) have gotten faster and faster. Thus, increasing reference clock signals in integrated circuits. Correspondingly, high speed integrated circuit designers are focusing on how to reduce clock skews and clock jitters. Since delay lock loops are easy to design and are stable, delay lock loops are commonly used for clock calibration. Delay lock loops and phase locked loops are commonly used in high speed digital circuits, such as microprocessors, memory interfaces and communication ICs. However, because chips are becoming more integrated and faster, power consumption has increased. Correspondingly, the question of “How to reduce power consumption of circuits in an integrated circuit?” have also become more and more important for circuit designers.